1. Field of the Invention
The present invention relates to a microcomputer, and particularly to a microcomputer, whereby execution of instructions by its CPU is sped up and a high speed operation is made possible at the time of processings such as resetting, interrupting and so on.
2. Description of the Related Art
FIG. 1 is a timing chart for explaining an example of basic instruction cycles, that is, a timing for executing a basic instruction of a conventional microcomputer.
In this conventional example, an input clock frequency is 40 MHz, in other words, a 25 ns cycle, and two basic clocks BCLK 1 and BCLK 2, obtained by further dividing the cycle into two to shift the phases of them, are used. A basic cycle for accessing a memory connected to the microcomputer corresponds to 100 ns which is two cycles of the basic clock (a machine cycle). Thus, an address signal (A) is that, a 100 ns period is basically treated as one cycle. In a read cycle shown in a left half side of FIG. 1, a data signal D becomes significant at 50 ns of a first half of the one basic cycle. In a write cycle shown in a right half side of FIG. 1, the data signal D is outputted from a CPU at 75 ns of the first half.
In general, basically a program memory is read by the same operation as the example shown in FIG. 1, and an instruction fetch is executed at a time (100 ns) of 4 cycles when based on the input clock.
FIG. 2 is a schematic view for explaining a principle of pipeline processing adopted in many microcomputers in recent years.
Based on the one machine cycle, processings in respective stages of an instruction fetch (IF), an instruction decoding (ID), an instruction execution and effective address calculation (EX), a memory access (MEM) and a write back (WB) are executed sequentially. Since instruction decodings are executed successively for every cycle, and continuously the instructions are processed respectively in parallel in respective stages, five instructions seem to be processed simultaneously in parallel as a whole. By such pipeline processing, complicated processings seem to be executed as if at one instruction per one machine cycle.
FIG. 3 is a schematic view showing an example of notes to be taken in the pipeline processings as described above. Specifically, mechanisms required when executing an instruction string consisting of the instructions ADD, SUB, AND, OR and XOR as shown in FIG. 3 are shown.
In FIG. 3, a symbol R immediately after each instruction specifies a destination register, and two Rs thereafter specify source registers holding operands.
That is, though the add instruction (ADD) which is a first instruction adds contents of a register R2 and a register R3 and stores (writes back) the result in a register R1, since a value stored in the register R1 is used in the second to fourth instructions, in respective execution cycles, before the result of the addition by the first add instruction is stored in the register R1, a bypass circuit which makes it usable is required in the CPU. And in the XOR instruction which is a fifth instruction, a value which is usually written back to the register R1 can be used finally.
As described above, in the conventional microcomputer, the one machine cycle itself is constituted by a plurality of clocks, causing a substantially long instruction execution cycle. This is a method employed for enhancing reliability in response to some problems on a board design such as a delay time, breaking of bus lines and so on in the board computer age.
Though the pipeline processing is a very effective designing method for executing the complicated instruction rapidly, as is also shown in the above-mentioned example, since particular circuits corresponding to some exceptional processings must be added, complicated circuits result.
Also, the CPU in the conventional microcomputer requires several cycles for processing the instruction fetch, decoding and execution, restricting improvement of the execution speed. However, since there is a limit to increase a clock frequency, it is necessary to consider how many processings can be executed in one cycle.
Furth rmore, in a highly functional microcomputer, though a method of executing a plurality of instructions in one cycle to enhance the processing capability such as a super scaler technique and the like is adopted at present, in a field of cost oriented micro-controller, a product having a high processing speed and a simple configuration leading to cost cut of chips is greatly desired. Particularly, in a real-time control field in which a response speed of several .mu.s is required as represented by an applicable field of motor control and the like, a simple and high-speed CPU is wanted rather than a CISC configuration including complex highly functional instructions.